Importing User IPs

In addition to IPs developed with the Library tools, the M3602A software allows for importing and integration of user custom IPs into a project. These different user IPs have to be developed by the user, using external FPGA tools. The M3602A software is not designed for developing IPs from scratch. However, once the user has finished creating an IP (synthesis and simulate it for example), the IP is ready for being imported to the M3602A software.

The user can import IPs from different source files:

VHDL source files.
Verilog source files.
Xilinx ISE projects.
Xilinx Vivado projects.
Matlab Simulink IPs designed using Xilinx System Generator.

To import a user IP, follow this process:

Click the icon in the toolbar, or find it in the File drop-down menu. In the image below, notice the file types that are available for importing. Notice also, the Relative path check box is checked by default.
Following the numbering in the image below, select the User IP icon, navigate to the file to be imported, and select it for importing into the project. Click OK to open and import the file.
The IP will be inserted into the project where it can be connected to other blocks. The block will have a blue background, see the blue block in the following image.
The file name will appear in the User IP External Block region for reuse as shown above. Note, these files can be removed by right-clicking the file name and choosing remove.

If the Relative Path check box is deselected, the path will become an absolute path.

If the User IP file is moved, an "X" will appear at the top of the block indicating the file cannot be found. Once the file is moved back, or the path changed, right-clicking the block will allow for reloading the IP and removing the "X" on the block.

If the underlying code for the code is changed, a "!" can appear to signify an alert condition. Once the code is corrected, the block can be reloaded to remove the "!" on the block.